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...Ececomplexdigitalasicdesign tutorial verilog hardware description language school of electrical and computer engineering cornell university revision contents introduction modeling synthesizable vs non rtl basics data types operators conditionals hello world logic shift arithmetic relational concatenation enumdatatypes struct ternary operator if statements case casez registered incrementer rtlmodelofregisteredincrementer simulating a model using iverilog verifying with unit testing reusingamodelwithstructuralcomposition parameterizing static elaboration sort flat sorter implementation usingveriloglinetraces structural evaluating the simulator greatest commondivisor verilogdesignexample control datapathsplit gcdunitusingasimulator in lab assignments for this course we will be pymtl framework functional level verication harnesses students can choose to use either or do their register transfer you are planning thenyoudonotneedtocompletethistutorial ifyouareplanningtouseverilog shouldstill ...